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armsd: list 0x8000
ARMProg
0x00008000: 0xe3a00001 .... : > mov r0,#1
0x00008004: 0xeb000005 .... : bl $Ven$AT$$ThumbProg
0x00008008: 0xe3a02003 . .. : mov r2,#3
0x0000800c: 0xe3a00018 .... : mov r0,#0x18
0x00008010: 0xe59f1000 .... : ldr r1,0x00008018 ; = #0x00020026
0x00008014: 0xef123456 V4.. : swi 0x123456
0x00008018: 0x00020026 &... : dcd 0x00020026 &...
ThumbProg
+0000 0x0000801c: 0x2102 .! : mov r1,#2
+0002 0x0000801e: 0x4770 pG : bx r14
$Ven$AT$$ThumbProg
+0000 0x00008020: 0xe59fc000 .... : ldr r12,0x00008028 ; = #0x0000801d
+0004 0x00008024: 0xe12fff1c ../. : bx r12
+0008 0x00008028: 0x0000801d .... : dcd 0x0000801d ....
+000c 0x0000802c: 0xe800e800 .... : dcd 0xe800e800 ....
+0010 0x00008030: 0xe7ff0010 .... : dcd 0xe7ff0010 ....
+0014 0x00008034: 0xe800e800 .... : dcd 0xe800e800 ....
+0018 0x00008038: 0xe7ff0010 .... : dcd 0xe7ff0010 ....
You can see that the linker has added the required ARM-to-Thumb interworking veneer. This is contained in
locations 0x8020 to 0x8028. Location 0x8028 contains the address of the routine being branch-exchanged to,
with bit 0 set, 0x801D.
3.4.2 C, C++, and assembly language interworking using veneers
C and C++ code compiled to run in one state can call assembly language code designed to run in the other state,
and vice versa. To do this, write the caller routine as any non-interworking routine and, if calling from assembly
language, use a BL instruction to make the call (see Example 3-7). Then:
• if the callee routine is in C, compile it using -apcs /interwork
• if the callee routine is in assembly language, assemble with the -apcs /interwork option and return using
BX lr.
Note
Any assembly language code or user library code used in this manner must conform to the ATPCS where
appropriate.
Example 3-7
/**********************
* thumb.c *
**********************/
#include <stdio.h>
extern int arm_function(int);
int main(void)
{
int i = 1;
printf("i = %d\n", i);
printf("And now i = %d\n", arm_function(i));
return (0);
}
; *****
; arm.s
; *****
AREA Arm,CODE,READONLY ; Name this block of code.
EXPORT arm_function
arm_function
ADD r0,r0,#4 ; Add 4 to first parameter.
BX LR ; Return
END
Follow these steps to build and link the modules:
1. Type tcc -c -apcs /interwork thumb.c to compile the Thumb code.
2. Type armasm -apcs /interwork arm.s to assemble the ARM code.
3. Type armlink arm.o thumb.o -o add to link the two object files.
Interworking ARM and Thumb
Copyright ?1999 2001 ARM Limited 3-9
- ARM® Developer Suite 1
- Version 1.2 1
- Developer Guide 1
- About this book 2
- ARM publications 3
- Other publications 3
- Feedback 4
- 1 Introduction 5
- Introduction 6
- 1.3 Developing for the ARM 7
- 1.3.5 Writing Code for ROM 8
- 2.1.1 ATPCS variants 9
- 2.1.2 ARM C libraries 9
- • Read-only memory 10
- 2.2 Register roles and names 11
- 2.3 The stack 12
- 2.4 Parameter passing 14
- 2.5 Stack limit checking 15
- 2.6.2 Writing code for ROPI 17
- 2.7.1 Reentrant routines 18
- 2.9 Floating-point options 20
- 3 Interworking ARM and Thumb 22
- 3.1 About interworking 22
- Interworking ARM and Thumb 23
- 3.2.3 Example ARM header 24
- Building the example 25
- 3.2.4 ARM architecture v5T 25
- 3.2.5 Labels in Thumb code 26
- C interworking example 27
- 5. Type go to run the code 31
- String copying example 33
- Operand expressions 33
- Physical registers 33
- 4.1.4 Usage 35
- 4.1.5 Examples 36
- Dot product 37
- Long multiplies 37
- • LDRB/STRB for char 39
- • LDR/STR for int 39
- C++ calling conventions 42
- C++ data types 42
- Symbol name mangling 43
- 4.4.3 Examples 43
- Calling C from C++ 44
- Calling C++ from C 45
- Handling Processor Exceptions 48
- • the address of the handler 53
- 5.4 SWI handlers 55
- Nested SWIs in C and C++ 57
- 5.5 Interrupt handlers 61
- • Single-channel DMA transfer 63
- • Dual-channel DMA transfer 63
- • Interrupt prioritization 63
- • Context switch 63
- Interrupt prioritization 64
- Context switch 65
- 5.6 Reset handlers 67
- 5.8 Prefetch Abort handler 69
- 5.9 Data Abort handler 70
- • A single extended handler 71
- • Several chained handlers 71
- Handling the exception 72
- 5.11.2 The return address 72
- FIQ and IRQ handlers 73
- Prefetch Abort handlers 73
- Data Abort handlers 73
- 5.12 System mode 75
- 6 Writing Code for ROM 76
- 6.2.1 ROM at 0x0 77
- 6.2.2 RAM at 0x0 77
- Implementing RAM at 0x0 77
- System decoder 78
- 6.3 Initializing the system 79
- 6.4.1 Memory map 81
- 6.4.2 Sample code 82
- • five execution regions: 83
- 6.5.3 Sample code 84
- 6.5.4 Building the example 88
- Using the CodeWarrior IDE 89
- Using the command line 89
- 6.6.1 Memory map 90
- 6.6.3 Initialization code 91
- 6.6.4 Building the example 91
- 6.7.1 Memory map 93
- 6.7.2 Building the example 93
- 6.7.3 Sample code 93
- 6.8.1 Memory map 97
- 6.8.2 Building the example 97
- 6.8.4 Sample code 98
- 6.9.2 Using unions 100
- Using an array of shorts 100
- Using a struct 100
- 6.9.4 Using scatter loading 101
- 6.9.5 Code efficiency 102
- 6.10 Troubleshooting 103
- Writing Code for ROM 104
- Code (or read-only) segments 105
- Data (or read-write) segments 105
- Debug data 105
- 7.1.1 About caches 106
- ARMulator Pagetable model 106
- 7.1.4 Cache performance 107
- 7.3 Memory protection units 109
- 7.4 Configuring a PU 110
- 7.5 Memory management units 113
- 7.6 Configuring an MMU 115
- 7.7 Tightly coupled memory 117
- 7.7.3 ARM966E-S warm reset 118
- Debug Communications Channel 120
- 8.4 Target transfer of data 123
- • Using armsd 125
- • Using AXD 125
- Issuing commands 126
- Using AXD 126
- 8.7 Access from Thumb state 129
- 8.8 Semihosting 130
- Glossary 131
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