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Noté. / 5. Basé sur avis des utilisateurs
• use literal pools
• set software breakpoints for debugging
• download code
• write self-modifying code.
Instruction fetches from data TCM are not allowed.
Warning
An attempt to load an instruction from data TCM might result in an access to off-chip memory at the same address.
This is core dependent. Refer to the Technical Reference manual for your processor.
7.7.2 Initializing the ARM966E-S
The initial configuration of the core is controlled by two input pins:
VINITHI
• HIGH, the vector table is located at 0xFFFF0000
• LOW, the vector table is located at 0x0.
INITRAM
• HIGH, TCM is enabled
• LOW, TCM is disabled.
These pins determine the configuration of the core on power-up, and on reset. You can override these configurations
in software by writing to CP15.
You can:
• Tie both INITRAM and VINITHI HIGH.
Execution starts at 0xFFFF0000. Boot code initializes TCM, then relocates the vector table to 0x0 for improved
performance.
• Tie INITRAM low, and VINITHI HIGH.
Execution starts at 0xFFFF0000. Boot code enables and initializes TCM, then relocates the vector table to 0x0
for improved performance.
• Tie both INITRAM and VINITHI LOW.
Execution starts at 0x0, in off-chip memory. Boot code must branch out of the bottom 128MB address range
before TCM can be enabled and initialized.
Caution
Do not tie INITRAM HIGH with VINITHI tied LOW. The result is unpredictable.
7.7.3 ARM966E-S warm reset
You can implement a warm reset running in TCM.
INITRAM and VINITHI can be controlled by memory-mapped registers. You can then have different behavior for
power-on reset and warm reset.
For example, both pins might be LOW for power on reset. Boot code reconfigures the warm reset behavior before
branching to the application.
You can implement a warm reset running in TCM.
To implement a warm reset:
• TCM must be initialized
• INITRAM must be HIGH
• VINITHI must be LOW.
7.7.4 ARM966E-S performance issues
The ARM966E-S runs at peak performance when:
• executing code contained in TCM
• accessing data contained in TCM
• the write buffer is enabled.
The ARM9E core stalls:
Caches and Tightly Coupled Memories
Copyright ?1999 2001 ARM Limited 7-13
- ARM® Developer Suite 1
- Version 1.2 1
- Developer Guide 1
- About this book 2
- ARM publications 3
- Other publications 3
- Feedback 4
- 1 Introduction 5
- Introduction 6
- 1.3 Developing for the ARM 7
- 1.3.5 Writing Code for ROM 8
- 2.1.1 ATPCS variants 9
- 2.1.2 ARM C libraries 9
- • Read-only memory 10
- 2.2 Register roles and names 11
- 2.3 The stack 12
- 2.4 Parameter passing 14
- 2.5 Stack limit checking 15
- 2.6.2 Writing code for ROPI 17
- 2.7.1 Reentrant routines 18
- 2.9 Floating-point options 20
- 3 Interworking ARM and Thumb 22
- 3.1 About interworking 22
- Interworking ARM and Thumb 23
- 3.2.3 Example ARM header 24
- Building the example 25
- 3.2.4 ARM architecture v5T 25
- 3.2.5 Labels in Thumb code 26
- C interworking example 27
- 5. Type go to run the code 31
- String copying example 33
- Operand expressions 33
- Physical registers 33
- 4.1.4 Usage 35
- 4.1.5 Examples 36
- Dot product 37
- Long multiplies 37
- • LDRB/STRB for char 39
- • LDR/STR for int 39
- C++ calling conventions 42
- C++ data types 42
- Symbol name mangling 43
- 4.4.3 Examples 43
- Calling C from C++ 44
- Calling C++ from C 45
- Handling Processor Exceptions 48
- • the address of the handler 53
- 5.4 SWI handlers 55
- Nested SWIs in C and C++ 57
- 5.5 Interrupt handlers 61
- • Single-channel DMA transfer 63
- • Dual-channel DMA transfer 63
- • Interrupt prioritization 63
- • Context switch 63
- Interrupt prioritization 64
- Context switch 65
- 5.6 Reset handlers 67
- 5.8 Prefetch Abort handler 69
- 5.9 Data Abort handler 70
- • A single extended handler 71
- • Several chained handlers 71
- Handling the exception 72
- 5.11.2 The return address 72
- FIQ and IRQ handlers 73
- Prefetch Abort handlers 73
- Data Abort handlers 73
- 5.12 System mode 75
- 6 Writing Code for ROM 76
- 6.2.1 ROM at 0x0 77
- 6.2.2 RAM at 0x0 77
- Implementing RAM at 0x0 77
- System decoder 78
- 6.3 Initializing the system 79
- 6.4.1 Memory map 81
- 6.4.2 Sample code 82
- • five execution regions: 83
- 6.5.3 Sample code 84
- 6.5.4 Building the example 88
- Using the CodeWarrior IDE 89
- Using the command line 89
- 6.6.1 Memory map 90
- 6.6.3 Initialization code 91
- 6.6.4 Building the example 91
- 6.7.1 Memory map 93
- 6.7.2 Building the example 93
- 6.7.3 Sample code 93
- 6.8.1 Memory map 97
- 6.8.2 Building the example 97
- 6.8.4 Sample code 98
- 6.9.2 Using unions 100
- Using an array of shorts 100
- Using a struct 100
- 6.9.4 Using scatter loading 101
- 6.9.5 Code efficiency 102
- 6.10 Troubleshooting 103
- Writing Code for ROM 104
- Code (or read-only) segments 105
- Data (or read-write) segments 105
- Debug data 105
- 7.1.1 About caches 106
- ARMulator Pagetable model 106
- 7.1.4 Cache performance 107
- 7.3 Memory protection units 109
- 7.4 Configuring a PU 110
- 7.5 Memory management units 113
- 7.6 Configuring an MMU 115
- 7.7 Tightly coupled memory 117
- 7.7.3 ARM966E-S warm reset 118
- Debug Communications Channel 120
- 8.4 Target transfer of data 123
- • Using armsd 125
- • Using AXD 125
- Issuing commands 126
- Using AXD 126
- 8.7 Access from Thumb state 129
- 8.8 Semihosting 130
- Glossary 131
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