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5 Handling Processor Exceptions

This chapter describes how to handle the various types of exception supported by ARM processors. It contains the

following sections:

• About processor exceptions

• Entering and leaving an exception

• Installing an exception handler

• SWI handlers

• Interrupt handlers

• Reset handlers

• Undefined Instruction handlers

• Prefetch Abort handler

• Data Abort handler

• Chaining exception handlers

• Handling exceptions on Thumb-capable processors

• System mode.

5.1 About processor exceptions

During the normal flow of execution through a program, the program counter increases sequentially through the

address space, with branches to nearby labels or branch and links to subroutines.

Processor exceptions occur when this normal flow of execution is diverted, to allow the processor to handle events

generated by internal or external sources. Examples of such events are:

• externally generated interrupts

• an attempt by the processor to execute an undefined instruction

• accessing privileged operating system functions.

It is necessary to preserve the previous processor status when handling such exceptions, so that execution of the

program that was running when the exception occurred can resume when the appropriate exception routine has

completed.

Table 5-1 shows the seven different types of exception recognized by ARM processors.

Table 5-1 Exception types

Exception Description

Reset Occurs when the processor reset pin is asserted. This exception is only

expected to occur for signalling power-up, or for resetting as if the

processor has just powered up. A soft reset can be done by branching to

the reset vector (

0x0000).

Undefined Instruction Occurs if neither the processor, or any attached coprocessor, recognizes

the currently executing instruction.

Software Interrupt (SWI) This is a user-defined synchronous interrupt instruction.It allows a program

running in User mode, for example, to request privileged operations that

run in Supervisor mode, such as an RTOS function.

Prefetch Abort Occurs when the processor attempts to execute an instruction that was not

fetched, because the address was illegal

An illegal virtual address is one that does not currently correspond to an

address in physical memory, or one that the memory management

subsystem has determined is inaccessible to the processor in its current

mode.

Data Abort Occurs when a data transfer instruction attempts to load or store data at

an illegal address

IRQ Occurs when the processor external interrupt request pin is asserted

(LOW) and the I bit in the CPSR is clear.

FIQ Occurs when the processor external fast interrupt request pin is asserted

(LOW) and the F bit in the CPSR is clear.

Handling Processor Exceptions

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