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• When you load from that region, the cache is searched. If the item is found, it is loaded from the cache. If the
item is not found, a complete cache line including the required address is loaded. Some other cache line is
evicted from the cache, unless there is an unused cache line available.
• When you save to that region, the cache is searched. If the item is found, the save is made to the cache. If the
item is not found, the save is made to memory.
The exact effect of the bufferable flag varies (see the Technical Reference Manual for your processor for details).
Bits [7:0] of register c2 in CP15 are the cacheable flags. Opcode 2 is used to select instruction or data regions.
Bits [7:0] of register c3 in CP15 are the bufferable flags. Opcode 2 must be 0 because bufferable flags can only be
used for data regions.
Operand2 specifies data or instruction regions.
Example 7-2 Setting cacheable and bufferable flags
MOV r0,#2_00011010 ; set data regions 1, 3 and 4 as cacheable, all others noncacheab
le
MCR p15,0,r0,c2,c0,0
MOV r0,#2_00010010 ; set instruction regions 1 and 4 as cacheable, all others noncac
heable
MCR p15,0,r0,c2,c0,1
MOV r0,#2_00001000 ; set data region 3 as write bufferable, all others nonbufferable
MCR p15,0,r0,c3,c0,0
7.4.3 Setting region access permissions
Coprocessor register c5 of CP15 is the region access permissions register. Example 7-3 sets Region access
permissions.
Operand2 specifies data or instruction regions.
Example 7-3 Setting access permissions
MOV r0,#2_1111111100 ; set data region 1, 2, 3 and 4 as full access
MCR p15,0,r0,c5,c0,0
MOV r0,#2_1000001000 ; set instruction region 1 and 4 as:
MCR p15,0,r0,c5,c0,1 ; Privileged Mode, full access; User Mode, read only
Table 7-1 and Table 7-2 show the meanings of the bits in the access permission register.
Table 7-1 Region bit mapping scheme
Register bit Function
[15:14] access permission bits [1:0] of
area 7
[13:12] access permission bits [1:0] of
area 6
[11:10] access permission bits [1:0] of
area 5
... ...
Table 7-2 Region access permission bit definition
bits [1:0] Meaning
00 No access
01 Access from privileged mode only
10 Full access from privileged mode, read only from
User mode
11 Full access
Note
Some processors have four bits per region (see the Technical Reference Manual for your processor for details).
Caches and Tightly Coupled Memories
Copyright ?1999 2001 ARM Limited 7-6
- ARM® Developer Suite 1
- Version 1.2 1
- Developer Guide 1
- About this book 2
- ARM publications 3
- Other publications 3
- Feedback 4
- 1 Introduction 5
- Introduction 6
- 1.3 Developing for the ARM 7
- 1.3.5 Writing Code for ROM 8
- 2.1.1 ATPCS variants 9
- 2.1.2 ARM C libraries 9
- • Read-only memory 10
- 2.2 Register roles and names 11
- 2.3 The stack 12
- 2.4 Parameter passing 14
- 2.5 Stack limit checking 15
- 2.6.2 Writing code for ROPI 17
- 2.7.1 Reentrant routines 18
- 2.9 Floating-point options 20
- 3 Interworking ARM and Thumb 22
- 3.1 About interworking 22
- Interworking ARM and Thumb 23
- 3.2.3 Example ARM header 24
- Building the example 25
- 3.2.4 ARM architecture v5T 25
- 3.2.5 Labels in Thumb code 26
- C interworking example 27
- 5. Type go to run the code 31
- String copying example 33
- Operand expressions 33
- Physical registers 33
- 4.1.4 Usage 35
- 4.1.5 Examples 36
- Dot product 37
- Long multiplies 37
- • LDRB/STRB for char 39
- • LDR/STR for int 39
- C++ calling conventions 42
- C++ data types 42
- Symbol name mangling 43
- 4.4.3 Examples 43
- Calling C from C++ 44
- Calling C++ from C 45
- Handling Processor Exceptions 48
- • the address of the handler 53
- 5.4 SWI handlers 55
- Nested SWIs in C and C++ 57
- 5.5 Interrupt handlers 61
- • Single-channel DMA transfer 63
- • Dual-channel DMA transfer 63
- • Interrupt prioritization 63
- • Context switch 63
- Interrupt prioritization 64
- Context switch 65
- 5.6 Reset handlers 67
- 5.8 Prefetch Abort handler 69
- 5.9 Data Abort handler 70
- • A single extended handler 71
- • Several chained handlers 71
- Handling the exception 72
- 5.11.2 The return address 72
- FIQ and IRQ handlers 73
- Prefetch Abort handlers 73
- Data Abort handlers 73
- 5.12 System mode 75
- 6 Writing Code for ROM 76
- 6.2.1 ROM at 0x0 77
- 6.2.2 RAM at 0x0 77
- Implementing RAM at 0x0 77
- System decoder 78
- 6.3 Initializing the system 79
- 6.4.1 Memory map 81
- 6.4.2 Sample code 82
- • five execution regions: 83
- 6.5.3 Sample code 84
- 6.5.4 Building the example 88
- Using the CodeWarrior IDE 89
- Using the command line 89
- 6.6.1 Memory map 90
- 6.6.3 Initialization code 91
- 6.6.4 Building the example 91
- 6.7.1 Memory map 93
- 6.7.2 Building the example 93
- 6.7.3 Sample code 93
- 6.8.1 Memory map 97
- 6.8.2 Building the example 97
- 6.8.4 Sample code 98
- 6.9.2 Using unions 100
- Using an array of shorts 100
- Using a struct 100
- 6.9.4 Using scatter loading 101
- 6.9.5 Code efficiency 102
- 6.10 Troubleshooting 103
- Writing Code for ROM 104
- Code (or read-only) segments 105
- Data (or read-write) segments 105
- Debug data 105
- 7.1.1 About caches 106
- ARMulator Pagetable model 106
- 7.1.4 Cache performance 107
- 7.3 Memory protection units 109
- 7.4 Configuring a PU 110
- 7.5 Memory management units 113
- 7.6 Configuring an MMU 115
- 7.7 Tightly coupled memory 117
- 7.7.3 ARM966E-S warm reset 118
- Debug Communications Channel 120
- 8.4 Target transfer of data 123
- • Using armsd 125
- • Using AXD 125
- Issuing commands 126
- Using AXD 126
- 8.7 Access from Thumb state 129
- 8.8 Semihosting 130
- Glossary 131
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