ARM Cortex R4F Manuel d'utilisateur télécharger pdf (Page 43)

Interrupt Latency Reduction

Time from interrupt request to the corresponding interrupt handler begins to

execute.

1. Suspend or Abandon Instruction Execution:

No need to suspend single cycle instruction but multiple cycle ones such as LDM,

STM, PUSH and POP that transfer multiple words to/from memory.

2. Late Arrival Processing:

CPU has begun an interrupt response sequence and another high priority interrupt

arrive during the stacking operation. The CPU will redirect the remainder of the

interrupt response so that it can handle the late arriving (higher priority) interrupt.

3. Tail Chaining:

In most CPUs when two ISRs execute back to back, the state information (8 word of

CPU state) is popped off the stack at the end of 1st interrupt only to be pushed back

at the beginning of the 2nd (next) interrupt.

M3 completely eliminates this useless pop-push sequence with a technique called

tail-chaining, lowering the ISR transition time from 24 down to 6 clock cycles.

CPSIE i ; Enable External Interrupts

CPSID i ; Disable External Interrupts

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ARM Cortex R4F Manuel d'utilisateur Page 43