ARM Cortex R4F Manuel d'utilisateur télécharger pdf (Page 15)

ARM CPU Features: Modified RISC

Multiple Load and Store Operation

Reduce the penalty of data accesses during a stall in the pipeline

Multiple load/store instructions can move any of the ARM registers

to and from memory, and update the memory address register

automatically after the transfer.

• This not only allows one instruction to transfer many words of

data (in a single bus burst), it also reduces the amount of

instructions needed to transfer data.

• Make the ARM code smaller than other 32-bit CPUs

• These instructions can specify an update of the base address

RISC CPU architectures would normally use a second instruction (add or

subtract) to form the next address in a sequence.

ARM does it automatically with a single bit in the instruction, again a

useful saving in code size.

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ARM Cortex R4F Manuel d'utilisateur Page 15