ARM ARM7TDMI Manuel d'utilisateur

ARM Cortex-M3 Processor Software Development for ARM7TDMI Processor Programmers Joseph Yiu and Andrew Frame July 2009 Overview Since its intro

[10] LDMDB R0!, {R1-R4} ; Read 4 words from memory address indicated by R0, pre-decrement R0 STMDB R0!, {R1,R4,R6} ; Write 3 words

[11] In ARM7TDMI processor assembler code accesses to the CPSR are required to switch between the different processor modes. In the simpler Cortex-

[12] Operation ARM7TDMI software (assembly and C) Porting to Cortex-M3 software (FIQ replaced by exception priority model) Enable IRQ MRS R0, CPS

[13] To port assembler code from ARM code to Cortex-M3 Thumb code, some of the branch and conditional branch instructions will need modification to

[14] In most applications, the fault handler might just reset the system itself or restart the offending process if it is running an operating syst

[15] PART C: Modifications for projects with Embedded OS and 3rd party libraries For software developed for the ARM7TDMI with an embedded OS, the e

[16] Appendix A C code vector table example. Exception vector table in C typedef void(* const ExecFuncPtr)(void) __irq; /* Linker-generated Stack

[17] exceptions.o (exceptions_area, +FIRST) } … Further examples can be found in the examples of RealView Development Suite installation (Co

[18] void SVCHandler_main(unsigned int * svc_args) { unsigned int svc_number; /* * Stack contains: * r0, r1, r2, r3, r12, r14, the return address a

[2] The switch to Cortex-M3 also makes software development easier because the Cortex-M3 processor includes a comprehensive set of debug and trace

[3] Idiom recognitions and intrinsic functions on C source code The Cortex-M3 processor provides a number of special instructions to increase the p

[4] Modification Scenarios The modifications required to enable ARM7TDMI processor software to run on a Cortex-M3 processor will depend on the comp

[5] PART A: Modifications for simple cases C code It is recommended that all C code be recompiled so that it can be both optimized for the more pow

[6] B IRQ_Handler B FIQ_Handler Reset_Handler ; Setup Stack for each mode LDR R0,=Stack_Top MSR CPSR_c, #Mode_IRQ:OR:I

[7] priority grouping (PRIGROUP) field. This allows the priority field in each priority register to be divided into pre-empt priority and sub-prior

[8] PART B: Modifications for projects with assembler code Projects with mixed C and assembler code may require additional modifications due to dif

[9] Swap (SWP) and Swap Byte (SWPB) instructions The SWP and SWPB instructions are used for atomic memory accesses, usually for semaphores or mutex