Arm VERSION 1.2 Manuel d'utilisateur télécharger pdf (Page 267)

100

101

Vector Floating-point Programming

6.7.10 FMDRR and FMRRD

Transfer contents between two ARM registers and a double-precision floating-point

Syntax

FMDRR{cond} Dn, Rd, Rn

FMRRD{cond} Rd, Rn, Dn

where:

cond

is an optional condition code (see VFP and condition codes on page 6-8).

is the VFP double-precision register.

Rd, Rn

are ARM registers. Do not use r15.

Usage

FMDRR Dn, Rd, Rn

transfers the contents of

into the low half of

, and the contents of

into the high half of

FMRRD Rd, Rn, Dn

transfers the contents of the low half of

into

, and the contents of

the high half of

into

Exceptions

These instructions do not produce any exceptions.

Architectures

These instructions are available in VFPv2 and above.

Examples

FMDRR d5, r3, r4

FMRRDPL r12, r2, d2

1 2 ... 262 263 264 265 266 267 268 269 270 271 272 ... 359 360

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Arm VERSION 1.2 Manuel d'utilisateur Page 267

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