ARM Cortex R4F Spécifications télécharger pdf (Page 8)

Standard Initialization Sequence for Hercules Microcontrollers

www.ti.com

| 0x00000020U // Enable clock source 5

| 0x00000040U; // Enable clock source 6

The above configuration enables clock sources 0, 1, 4, 5, and 6.

Of the clock sources that are enabled, number 0, 4 and 5 are enabled by default and will have become

valid by the time the processor is released from reset upon a power-up. These are the main oscillator and

the two outputs from the internal reference oscillator.

Clock source 1 and 6 are the two PLL outputs. The FMPLL as well as the FMPLL#2 have a defined start-

up time, and their outputs are not available for use until this time. The application must wait for the valid

status flags for these clock sources to be set before using the PLL outputs for any clock domain. The

example initialization sequence makes use of this PLL lock time to perform all initialization actions that

don'e have to be done at the maximum operating frequency chosen for the application.

2.9 Run Self-Test on the eFuse Controller SECDED Logic

Electrically programmable fuses (eFuses) are used to configure the part after de-assertion of power-on

reset (nPORRST). The eFuse values are read and loaded into internal registers as part of the power-on-

reset sequence. This is called the eFuse autoload. The eFuse values are protected with single-bit error-

correction, double-bit error-detection (SECDED) codes. These fuses are programmed during the initial

factory test of the device. The eFuse controller is designed so that the state of the eFuses cannot be

changed once the device is packaged.

For safety critical systems, it is important for the application to check the status of the eFuse controller

after a device reset. For more details on eFuse controller errors and the application sequence to check for

these errors, see the eFuse Controller chapter of the device-specific technical reference manual.

2.10 Release Reset and Clocks to Peripherals

The peripherals are kept under reset, and need to be explicitly brought out of reset by the application. This

can be done by setting the peripheral enable (PENA) bit of the Clock Control Register (CLKCNTL).

The clocks to the peripheral modules are also disabled upon any system reset and need to be explicitly

enabled by the application. This can be done by setting the bits corresponding to the peripheral select

quadrant occupied by the peripheral module in the Peripheral Central Resource (PCR) Control Registers

for clearing the power down states of peripheral modules (Peripheral Power-Down Clear Register [0:3]

(PSPWRDWNCLRx)). For information on the peripheral select quadrants for each peripheral, see the

device-specific data sheet.

2.11 Configure Flash Access

The Flash memory on the Hercules series microcontrollers is a non-volatile electrically erasable and

programmable memory.

The Hercules microcontrollers contain a digital module that manages all accesses to the Flash memory. A

Flash access can be completed without any wait states required for bus master clock speeds up to 45

MHz. If the bus clock is faster than 45 MHz, then any Flash access requires the appropriate number of

wait states depending on the bus clock speed. The Hercules series microcontrollers support clock speeds

up to 180 MHz. For the actual maximum allowed speed and the number of corresponding address and

data wait states, see the device-specific data sheet.

Suppose that the application requires a CPU clock speed of 180 MHz. This requires 1 address wait state

and 3 data wait states for any access to the Flash memory. These wait states need to be configured in the

Flash module registers.

The Flash module also features a pipelined mode of operation. When this mode is enabled, the module

reads 128 bits from the Flash memory and holds them in buffers that the CPU can read from without any

wait state. The CPU can read 32 or 64 bits of instructions or data from the pipeline buffers.

The Flash Read Control Register (FRDCNTL) inside the Flash module controls the wait states and the

pipeline mode.

Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers SPNA106D–May 2013

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