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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
DocID024647 Rev 1 49/138
RM0352 ARM
©
dual timer module (SP804)
137
The dual timer module consists of two identical programmable “Free Running Counters”
(FRCs) that can be configured for 32-bit or 16-bit operation and one of three timer modes:
• Free running
• Periodic
• One-shot.
The FRCs operate from a common timer clock, TIMCLK with each FRC having its own clock
enable input, TIMCLKEN1 and TIMCLKEN2. Each FRC also has a prescaler that can divide
down the enabled TIMCLK rate by 1, 16, or 256. This enables the count rate for each FRC
to be controlled independently using their individual clock enables and prescalers.
TIMCLK can be equal to or be a submultiple of the PCLK frequency. However, the positive
edges of TIMCLK and PCLK must be synchronous and balanced.
The operation of each Timer module is identical. A Timer module can be programmed for
a 32-bit or 16-bit counter size and one of three timer modes using the control register. The
three timer modes are:
Free running The counter operates continuously and wraps around to its maximum
value each time that it reaches zero.
Periodic The counter operates continuously by reloading from the load register
each time that the counter reaches zero.
One-shot The counter is loaded with a new value by writing to the load register.
The counter decrements to zero and then halts until it is reprogrammed.
The timer count is loaded by writing to the load register and, if enabled, the timer count
decrements at a rate determined by TIMCLK, TIMCLKENX, and the prescaler setting. When
the Timer counter is already running, writing to the load register causes the counter to
immediately restart from the new value.
An alternative way of loading the Timer count is by writing to the background load register.
This has no immediate effect on the current count but the counter continues to decrement.
On reaching zero, the Timer count is reloaded from the new load value if it is in periodic
mode.
When the Timer count reaches zero an interrupt is generated. The interrupt is cleared by
writing to the interrupt clear register. The external interrupt signals can be masked off by the
interrupt mask registers.
The current counter value can be read from the value register at any time.
- Reference manual 1
- Contents 2
- DocID024647 Rev 1 3/138 3
- 4/138 DocID024647 Rev 1 4
- DocID024647 Rev 1 5/138 5
- 6/138 DocID024647 Rev 1 6
- List of tables 7
- 8/138 DocID024647 Rev 1 8
- DocID024647 Rev 1 9/138 9
- List of figures 10
- 1 Referenced document 11
- 2 System and memory overview 12
- 2.2 Memory organization 13
- 2.3 Embedded SRAM 15
- 2.4 Flash memory overview 15
- 2.5 Physical remap 16
- Interrupts RM0352 18
- Table 3. Interrupt vectors 18
- (continued) 18
- 5.1 Introduction 21
- 5.2 Clock generation 21
- Figure 2. Clock generation 22
- DocID024647 Rev 1 23/138 23
- 5.3 Reset generation 24
- 5.3.2 Power-on reset 25
- 5.3.3 ECC reset 25
- 5.3.4 Watchdog reset 25
- 5.3.5 System reset request 26
- 5.3.6 Lockup reset 26
- 5.3.7 Recall done 26
- 6.3.4 Command register 34
- MASS ERASE 34
- DocID024647 Rev 1 37/138 37
- 0-Unlocked 37
- 1NoLocked 37
- 1 Yes Unlocked 37
- Watchdog timer (WDG) RM0352 40
- Table 26. WDG register list 40
- dual timer module (SP804) 47
- 8.2 Functional overview 48
- DocID024647 Rev 1 49/138 49
- 8.2.2 Functional description 50
- Free running counter blocks 51
- Interface reset 51
- Prescaler operation 52
- Timer operation 53
- 54/138 DocID024647 Rev 1 54
- Interrupt behavior 55
- 56/138 DocID024647 Rev 1 56
- 8.3 Programmer's model 57
- 8.3.2 Register descriptions 59
- Load register, TimerXLoad 60
- ". 63
- 9.4 Configuring SysTick 70
- C bus interface RM0352 72
- Table 70. I 72
- C register list 72
- 74/138 DocID024647 Rev 1 74
- DocID024647 Rev 1 75/138 75
- 76/138 DocID024647 Rev 1 76
- 78/138 DocID024647 Rev 1 78
- 10.2.5 I 80
- C status register (I2C_SR) 80
- DocID024647 Rev 1 81/138 81
- 82/138 DocID024647 Rev 1 82
- DocID024647 Rev 1 87/138 87
- DocID024647 Rev 1 89/138 89
- 90/138 DocID024647 Rev 1 90
- DocID024647 Rev 1 91/138 91
- 11.1 Features 100
- 11.2 Clock prescaler 100
- 101
- 11.5.4 SSPRTINTR 114
- 11.5.1 SSPRXINTR 114
- 11.5.2 SSPTXINTR 114
- 11.5.3 SSPRORINTR 114
- 12.1 Features 115
- 12.2 IrDA SIR block 116
- 12.3 Baud rate generator 116
- 12.4 Interrupts 116
- 12.4.1 UARTMSINTR 117
- 12.4.2 UARTRXINTR 117
- 12.4.3 UARTTXINTR 117
- 12.5 UART registers 118
- 12.6 Register descriptions 120
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